Delta-sigma modulator for analog-to-digital converting is a key building block of modern signal/audio/video processing circuits and communication circuits. Delta-sigma ADC is based on the technique of oversampling to reduce the noise in the band of interest. With oversampling, the quantizer within the delta-sigma ADC may be a simple ADC with lower resolution to be cost effective.
Since real circuit blocks always introduce some time delay in performing sampling, quantization, and digital-to-analog conversion, excess loop delay (ELD) is a well known non-ideality of continuous-time delta-sigma modulators. ELD is an important concern in high sampling rate delta-sigma modulators due to its detrimental effect on performance and stability. Thus there is a need for a technique for dealing with the ELD problem.